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| Partname: | IDT71V546S117PFI |
| Description: | 128K x 36, 3.3V Synchronous SRAM with ZBT Feature, Burst Counter and Pipelined Outputs |
| Manufacturer: | Integrated Device Technology |
| Datasheet: | PDF (178K).
Click here to download *) |
The IDT71V546 contains data I/O, address and control signal registers. Output enable is the only asynchronous signal and can be used to disable the outputs at any given time. A Clock Enable (CEN) pin allows operation of the IDT71V546 to be suspended as long as necessary. All synchronous inputs are ignored when CEN is high and the internal device registers will hold their previous values. |
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Click here to download IDT71V546S117PFI Datasheet*) |
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