The IDT71V433 SRAM contains write, data-input, address and control registers. There are no registers in the data output path (flowthrough architecture). Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the extreme end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as the IDT71V433 can provide four cycles of data for a single address presented to the SRAM. An internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will flow-through from the array after a clock-to-data access time delay from the rising clock edge of the same cycle. If burst mode operation is selected (ADV=LOW), the subsequent three cycles of output data will be available to the user on the next three rising clock edges. The order of these three addresses will be defined by the internal burst counter and the LBO input pin.