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Partname: | IDT71V3558S133BGG |
Description: | 128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs |
Manufacturer: | Integrated Device Technology |
Datasheet: | PDF (0.98M). Click here to download *) |
The IDT71V3556/58 contain data I/O, address and control signal registers. Output enable is the only asynchronous signal and can be used to disable the outputs at any given time. A Clock Enable (CEN) pin allows operation of the IDT71V3556/58 to be suspended as long as necessary. All synchronous inputs are ignored when (CEN) is high and the internal device registers will hold their previous values. |
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![Click here to download IDT71V3558S133BGG Datasheet](../../../pndecoder/datasheets/IDT/img/000513.gif) Click here to download IDT71V3558S133BGG Datasheet*) |
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