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Partname:IDT54FCT88915TT133PY
Description:Low skew PLL-based CMOS clock driver (with 3-state)
Manufacturer:Integrated Device Technology
Package:SSOP
Pins:28
Oper. temp.:-55 to 125
Datasheet:PDF (140K).
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The FREQ_SEL control provides an additional 2 option in the output path. PLL _EN allows bypassing of the PLL, which is useful in static test modes. When PLL_EN is low, SYNC input may be used as a test clock. In this test mode, the input frequency is not limited to the specified range and the polarity of outputs is complementary to that in normal operation (PLL_EN = 1). The LOCK output attains logic HIGH when the PLL is in steady-state phase and frequency lock. When OE/ RST is low, all the outputs are put in high impedance state and registers at Q, Q and Q/2 outputs are reset. The IDT54/74FCT88915TT requires one external loop filter component as recommended in Figure 1.

Click here to download IDT54FCT88915TT133PY Datasheet
Click here to download IDT54FCT88915TT133PY Datasheet
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