The IDT54/74FCT820 series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider address/data paths or buses carrying parity. The IDT54/ 74FCT821 are buffered, 10-bit wide versions of the popular `374 function. The IDT54/74FCT823 and IDT54/74FCT824 are 9-bit wide buffered registers with Clock Enable (EN) and Clear (CLR) ideal for parity bus interfacing in high-performance microprogrammed systems. The IDT54/74FCT825 are 8-bit buffered registers with all the `823 controls plus multiple enables (OE1, OE2, OE3) to allow multiuser control of the interface, e.g., CS, DMA and RD/WR. They are ideal for use as an output port requiring HIGH IOL/IOH. All of the IDT54/74FCT800 high-performance interface family are designed for high-capacitance load drive capability, while providing low-capacitance bus loading at both inputs and outputs. All inputs have clamp diodes and all outputs are designed for low-capacitance bus loading in high-impedance state.