The FCT823 series is built using an advanced dual metal CMOS technology. The FCT823 bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider address/data paths or buses carrying parity. The FCT823 is a 9-bit wide buffered register with Clock Enable (EN) and Clear (CLR) ideal for parity bus interfacing in high-performance microprogrammed systems. The FCT823 high-performance interface family is designed for highcapacitance load drive capability, while providing low-capacitance bus loading at both inputs and outputs. All inputs have clamp diodes and all outputs are designed for low-capacitance bus loading in high-impedance state.