The IDT2305A is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2305A is an 8-pin version of the IDT2309A. IDT2305A accepts one reference input, and drives out five low skew clocks. The -1H version of this device operates up to 133MHz frequency and has a higher drive than the -1 device. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. In the absence of an input clock, the IDT2305A enters power down. In this mode, the device will draw less than 12A for Commercial Temperature range and less than 25A for Industrial temperature range, the outputs are tri-stated, and the PLL is not running, resulting in a significant reduction of power.