The M844 Multi-Rate Clock Recovery module provides low jitter clock recovery from NRZ or RZ input data formats. Four data rates are digitally selectable: 9.953, 10.3125, 10.664, or 10.709Gb/s. Incoming data is first amplified by a limiting amplifier. The data is then both: a) provided as the module's unretimed data output, and b) applied to the clock recovery circuitry. A Phase Locked Loop (PLL) incorporates frequency multipliers and a SAW-based Voltage Control SAW Oscillator (VCSO) to minimize clock jitter. The VCSO provides the high Q, low noise, and high stability needed for the narrow bandwidth PLL operation. Micro-strip bandpass filters are used to produce sinusodal clock output with low harmonic and sub-harmonic distortion.