The ICS9112-18 is a low jitter, low-skew, high performance PLL based zero delay buffer for high speed applications. Based on ICS's proprietary low jitter Phase Locked Loop (PLL) techniques, the device provides eight low skew outputs at speeds up to 160 MHz at 3.3 V. The ICS9112-18 includes a bank of four outputs running at 1X, and another four outputs running at 1/2X. In the zero delay mode, the rising edge of the input clock is aligned with the rising edges of all eight outputs. Compared to competitive CMOS devices, the ICS9112-18 has the lowest jitter of all.