The VCXO PLL has an on-chip VCXO circuit that uses an external, inexpensive pullable crystal in the 17.5 to 25MHz range. The PLL includes 13 bit reference and feedback dividers supporting complex PLL multiplication ratios and input reference clock rates as low as 2.3kHz. External loop filter components are used (two resistors and two capacitors) to achieve the low loop bandwidth needed for jitter attenuation of a recovered data clock.