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| Partname: | ICS507M-01-DWF |
| Description: | PECL clock synthesizer |
| Manufacturer: | |
| Package: | SOIC |
| Pins: | 16 |
| Oper. temp.: | 0 to 70 |
| Datasheet: | PDF (49K).
Click here to download *) |
The ICS507-01 and ICS507-02 are inexpensive ways to generate a low jitter 155.52 MHz (or other high speed) differential PECL clock output from a low frequency crystal input. Using Phase-LockedLoop (PLL) techniques, the devices use a standard fundamental mode crystal to produce output clocks up to 200 MHz. |
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