The HD74HCT137 implements a three-to-eight line decoder with latches on the three address inputs. When G L goes from low to high, the address present at the select inputs (A, B and C) is stored in the latches. As long as G L remains high no address changes will be recognized. Output enable controls, G1 and G2, control the state of the outputs independently of the select or latch-enable inputs. All of the outputs are high unless G1 is high and G2 is low. The HD74HCT137 is ideally suited for the implementation of glitchfree decoders in stored-address applications in bus oriented systems.