These bus transceivers are designed for a synchronous three-way communication between four-line data buses. They give the designer a choice of selecting inverting, noninverting or a combination of inverting and noninverting data paths with 3-state outputs. The S 0 and S1 inputs select the bus from which data are to be transferred. The G inputs enable the bus or buses to which data are to be transferred. The port for any bus selected for input and any other bus not enabled for output will be at high impedance.