The HD74HC160 and the HD74HC162 are 4 bit decade counters, and the HD74HC161 and the HD74HC163 are 4 bit binary counters All flip-flops are clocked simultaneously on the low to high to transition (positive edge) of the clock input waveform. These counters may be preset using the load input. Presetting of all four flip-flops is synchronous to thte rising edge of clock. When load is held low counting is disabled and the data on the A, B, C, and D inputs is loaded into the counter on the rising edge of clock. If the load input is taken high before the positive edge of clock the count operation will be unaffected. All of these counters may be cleared by utilizing the clear input. The clear function on the HD74HC162 and HD74HC163 counters are synchronous to the clock. That is, the counters are cleared on the positive edge of clock while the clear input is held low. The HD74HC160 and HD74HC161 counters are cleared asynchronously. When the clear is taken low the counter is cleared immediately regardless of the clock. Two active high enable inputs Enable P and Enable T and a ripple carry output are provided to enable easy cascading of counters. Both enable inputs must be high to count. The Enable T input also enables the Ripple Carry output. When enabled, the Ripple Carry outputs a positive pulse when the counter overflows. This pulse is approximately equal in duration to the high level portion of the Q A outputs. The Ripple Carry output is fed to successive cascaded stages to facilitate easy implementation of N-bit counters.