The HD74ALVCH16835 is an 18-bit universal bus driver designed for 2.3 V to 3.6 V V CC operation. Data flow from A to Y is controlled by the output enable (OE ). The device operates in the transparent mode when the latch enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If the LE is low, the A bus data is stored in the latch/flip flop on the low to high transition of CLK. When O E is high, the outputs are in the high impedance state. To ensure the high impedance state during power up or power down, the output ebable ( OE) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current sinking capability of the driver. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.