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Partname:GS840H32AT-100I
Description:100MHz 12ns 128K x 32 4Mb sync burst SRAM
Manufacturer:
Package:TQFP
Pins:100
Oper. temp.:-40 to 85
Datasheet:PDF (910K).
Click here to download *)

The function of the Data Output register can be controlled by the user via the FT mode pin/bump (Pin 14 in the TQFP and Bump 5R in the BGA, ). Holding the FT mode pin/bump low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-dge-triggered Data Output Register.

Click here to download GS840H32AT-100I Datasheet
Click here to download GS840H32AT-100I Datasheet
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