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| Partname: | GS84018AB-100 |
| Description: | 100MHz 12ns 256K x 18 4Mb sync burst SRAM |
| Manufacturer: | |
| Package: | BGA |
| Pins: | 119 |
| Oper. temp.: | 0 to 70 |
| Datasheet: | PDF (911K).
Click here to download *) |
The function of the Data Output register can be controlled by the user via the FT mode pin/bump (pin 14 in the TQFP and bump 5R in the BGA). Holding the FT mode pin/bump low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipelined mode, activating the rising-edge-triggered Data Output Register. |
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Click here to download GS84018AB-100 Datasheet*) |
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