The GS9002 is a monolithic bipolar integrated circuit designed to serialize SMPTE 125M and SMPTE 244M bit parallel digital signals as well as other 8 or 10 bit parallel formats. This device performs the functions of sync detection, parallel to serial conversion, data scrambling (using the X9 + X4 +1 algorithm), 10x parallel clock multiplication and conversion of NRZ to NRZI serial data. It supports any of four selectable serial data rates from 100 Mb/s to over 360 Mb/s. The data rates are set by resistors and are selected by an on-board 2:4 decoder having two TTL level input address lines.