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Partname: | GTLP18T612G |
Description: | 18-Bit LVTTL/GTLP Universal Bus Transceiver |
Manufacturer: | Fairchild Semiconductor |
Package: | BGA |
Pins: | 54 |
Datasheet: | PDF (104K). Click here to download *) |
The GTLP18T612 is an 18-bit universal bus transceiver which provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data transfer. The device provides a high speed interface for cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP's reduced output swing (< 1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor logic (GTL) JEDEC standard JESD8-3. |
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Click here to download GTLP18T612G Datasheet*) |
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