The LVTH16835 consists of 18-bit universal bus drivers which combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. Data flow from A to Y is controlled by the output-enable (OE) input. This device operates in the transparent mode when the latch-enable (LE) input is HIGH. The A data is latched if the clock (CLK) input is held at a HIGH or LOW logic level. If LE is LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of the CLK. When OE is HIGH, the outputs are in the high-impedance state.