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| Partname: | 74F113SC |
| Description: | Dual JK Negative Edge-Triggered Flip-Flop |
| Manufacturer: | Fairchild Semiconductor |
| Package: | SOIC |
| Pins: | 14 |
| Datasheet: | PDF (59.8K).
Click here to download *) |
The 74F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the flipflop will perform according to the Truth Table as long as minimum setup and hold times are observed. Input data is |
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Click here to download 74F113SC Datasheet*) |
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