The PBL 40310 is a highly integrated single-ended silicon MMIC power amplifier intended for use in GSM terminals. It delivers 35 dBm at 900 MHz with 55 % power added efficiency into a 50 unbalanced load using a single 3.5 V supply. The circuit has an analog ramp signal to control output power level and a logical on/ off signal for power down mode. It can be used in dual-band amplifiers using the band select logical signal. It can be operated up to 50 % duty cycle with minimum performance degradation. The circuit is housed in a specially designed QSOP16 (150 mil body) package and the implementation requires only few external components. 25 GHz ft state-of-the-art deep trench isolated double-poly silicon bipolar process with additional features for improved wireless performance has been used. On-chip capacitors and inductors are used for the integrated internal matching network. Special front-side metallized substrate contacts provide excellent ground paths from active devices to the highly doped semiconductor substrate and package ground.