The PD45128163 are high-speed 134,217,728-bit synchronous dynamic random-access memories, organized as 2,097,152 x 16 x 4 (word x bit x bank). The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All inputs and outputs are synchronized with the positive edge of the clock. The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL). These products are packaged in 54-pin TSOP (II).