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| Partname: | HM5425401BTT-75A |
| Description: | 256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword ?? 16-bit ?? 4-bank/8-Mword ?? 8-bit ?? 4-bank/ 16-Mword ?? 4-bit ?? 4-bank |
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| Datasheet: | PDF (489K).
Click here to download *) |
The HM5425161B, the HM5425801B and the HM5425401B are the Double Data Rate (DDR) SDRAM devices. Read and write operations are performed at the cross points of the CLK and the C LK. This high speed data transfer is realized by the 2-bit prefetch piplined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode resistor, the on-chip Delay Locked Loop (DLL) can be set enable or disable. |
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Click here to download HM5425401BTT-75A Datasheet*) |
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