The HB54A2569F1U, HB54A5129F2U are Double Data Rate (DDR) SDRAM Module, mounted 256M bits DDR SDRAM (HM5425801BTT) sealed in TSOP package, and 1 piece of serial EEPROM (2k bits EEPROM) for Presence Detect (PD). The HB54A2569F1U is organized as 32M x 72 x 1 bank mounted 9 pieces of 256M bits DDR SDRAM. The HB54A5129F2U is organized as 32M x 72 x 2 banks mounted 18 pieces of 256M bits DDR SDRAM. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. An outline of the products is 184-pin socket type package (dual lead out). Therefore, it makes high density mounting possible without surface mount technology. It provides common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the module board.