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| Partname: | EDD5108AFTA_06 |
| Description: | 512M bits DDR SDRAM |
| Manufacturer: | |
| Datasheet: | PDF (488K).
Click here to download *) |
The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver Data inputs, outputs, and DM are synchronized with DQS |
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Click here to download EDD5108AFTA_06 Datasheet*) |
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