The EDD2508AMTA-5 is a 256M bits Double Data Rate (DDR) SDRAM organized as 8,388,608 words x 8 bits x 4 banks. The EDD2516AMTA-5 is a 256M bits DDR SDRAM organized as 4,194,304 words x 16 bits x 4 banks. Read and write operations are performed at the cross points of the CK and the /CK. This highspeed data transfer is realized by the 2 bits prefetchpipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode resister, the on-chip Delay Locked Loop (DLL) can be set enable or disable. They are packaged in standard 66pin plastic TSOP (II).