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Partname: | EDD2508AETA-5C-E |
Description: | 256M bits DDR SDRAM |
Manufacturer: | |
Datasheet: | PDF (576K). Click here to download *) |
The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver Data inputs, outputs, and DM are synchronized with DQS |
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![Click here to download EDD2508AETA-5C-E Datasheet](../../../pndecoder/datasheets/ELPID/img/000198.gif) Click here to download EDD2508AETA-5C-E Datasheet*) |
![](http://www.chipdocs.com/common/img/1x10t.gif) |
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