The EDD2504AJ is a 256M bits Double Data Rate (DDR) SDRAM organized as 16,777,216 words x 4 bits x 4 banks. The EDD2508AJ is a 256M bits DDR SDRAM organized as 8,388,608 words x 8 bits x 4 banks. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode resistor, the on-chip Delay Locked Loop (DLL) can be set enable or disable. They are packaged in standard 66-pin plastic TSOP (II).