The CY7C1049AV33GVT73512A8 is organized as a 262,144 x 16 SRAM using a four-transistor memory cell with a high-performance, silicon gate, low-power CMOS process. Cypress SRAMs are fabricated using double-layer polysilicon, double-layer metal technology. This device offers center power and ground pins for improved performance and noise immunity. Static design eliminates the need for external clocks or timing strobes. For increased system flexibility and eliminating bus contention problems, this device offers Chip Enable (CE), separate Byte Enable controls (BLE and BHE) and Output Enable (OE ) with this organization. The device offers a low-power standby mode when chip is not selected. This allows system designers to meet low standby power requirements.