The CY7C42X1 are high-speed, low-power FIFO memories with clocked Read and Write interfaces. All are 9 bits wide. The CY7C42X1 are pin-compatible to IDT722X1. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering. These FIFOs have 9-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock (WCLK) and two Write-enable pins (WEN1, WEN2/LD). When WEN1 is LOW and WEN2/LD is HIGH, data is written into the FIFO on the rising edge of the WCLK signal. While WEN1, WEN2/LD is held active, data is continually written into the FIFO on each WCLK cycle. The output port is controlled in a similar manner by a free-running Read clock (RCLK) and two Read-enable pins (REN1, REN2). In addition, the CY7C42X1 has an output enable pin (OE). The Read (RCLK) and Write (WCLK) clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous Read/Write applications. Clock frequencies up to 100 MHz are achievable.