The CY7C1392CV18, CY7C1992CV18, CY7C1393CV18, and CY7C1394CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with Double Data Rate Separate IO (DDR-II SIO) architecture. The DDR-II SIO consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. The DDR-II SIO has separate data inputs and data outputs to completely eliminate the need to "turn-around" the data bus required with common IO devices. Access to each port is accomplished through a common address bus. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with two 8-bit words in the case of CY7C1392CV18, two 9-bit words in the case of CY7C1992CV18, two 18-bit words in the case of CY7C1393CV18, and two 36-bit words in the case of CY7C1394CV18 that burst sequentially into or out of the device.