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Partname:CY7C1520AV18-278BZXC
Description:72-Mbit DDR-II SRAM 2-Word Burst Architecture
Manufacturer:Cypress Semiconductor
Datasheet:PDF (691K).
Click here to download *)

The CY7C1516AV18, CY7C1527AV18, CY7C1518AV18, and CY7C1520AV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with two 8-bit words in the case of CY7C1516AV18 and two 9-bit words in the case of CY7C1527AV18 that burst sequentially into or out of the device. The burst counter always starts with a "0" internally in the case of CY7C1516AV18 and CY7C1527AV18. On CY7C1518AV18 and CY7C1520AV18, the burst counter takes in the least significant bit of the external address and bursts two 18-bit words in the case of CY7C1518AV18 and two 36-bit words in the case of CY7C1520AV18 sequentially into or out of the device.

Click here to download CY7C1520AV18-278BZXC Datasheet
Click here to download CY7C1520AV18-278BZXC Datasheet
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