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Partname:CY7C1465AV33-100BGI
Description:36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL??? Architecture
Manufacturer:Cypress Semiconductor
Datasheet:PDF (1.10M).
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The CYP(V)15G0403DXB[1] Independent Clock Quad HOTLink IITM Transceiver is a point-to-point or point-to-multipoint communications building block enabling transfer of data over a variety of high-speed serial links like optical fiber, balanced, and unbalanced copper transmission lines. The signaling rate can be anywhere in the range of 195 to 1500 MBaud per serial link. Each channel operates independently with its own reference clock allowing different rates. Each transmit channel accepts parallel characters in an Input Register, encodes each character for transport, and then converts it to serial data. Each receive channel accepts serial data and converts it to parallel data, decodes the data into characters, and presents these characters to an Output Register. Figure 1 on page 2 illustrates typical connections between independent host systems and corresponding CYP(V)(W)15G0403DXB chips

Click here to download CY7C1465AV33-100BGI Datasheet
Click here to download CY7C1465AV33-100BGI Datasheet
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