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Partname: | CY7C1418BV18-250BZC |
Description: | 36-Mbit DDR-II SRAM 2-Word Burst Architecture |
Manufacturer: | Cypress Semiconductor |
Datasheet: | PDF (672K). Click here to download *) |
The CY7C1416BV18, CY7C1427BV18, CY7C1418BV18, and CY7C1420BV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with two 8-bit words in the case of CY7C1416BV18 and two 9-bit words in the case of CY7C1427BV18 that burst sequentially into or out of the device. The burst counter always starts with a "0" internally in the case of CY7C1416BV18 and CY7C1427BV18. On CY7C1418BV18 and CY7C1420BV18, the burst counter takes in the least significant bit of the external address and bursts two 18-bit words in the case of CY7C1418BV18 and two 36-bit words in the case of CY7C1420BV18 sequentially into or out of the device. |
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![Click here to download CY7C1418BV18-250BZC Datasheet](../../../pndecoder/datasheets/CYPR/img/001109.gif) Click here to download CY7C1418BV18-250BZC Datasheet*) |
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