The CY7C1411BV18, CY7C1426BV18, CY7C1413BV18, and CY7C1415BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDRTM-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The read port has dedicated data outputs to support the read operations and the write port has dedicated data inputs to support the write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to "turn-around" the data bus required with common IO devices. Access to each port is through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the QDR-II read and write ports are completely independent of one another. To maximize data throughput, read and write ports are equipped with DDR interfaces. Each address location is associated with four