The CY7C1370BV25 and CY7C1372BV25 SRAMs are designed to eliminate dead cycles when transitions from READ to WRITE or vice versa. These SRAMs are optimized for 100 percent bus utilization and achieves Zero Bus Latency. They integrate 524,288 x 36 and 1,048,576 x 18 SRAM cells, respectively, with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced single layer polysilicon, threelayer metal technology. Each memory cell consists of six transistors.