The CY7C1354DV25 and CY7C1356DV25 are 2.5V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus LatencyTM (NoBLTM) logic, respectively. They are designed to support unlimited true back to back read and write operations with no wait states. The CY7C1354DV25 and CY7C1356DV25 are equipped with the advanced (NoBL) logic required to enable consecutive read and write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent write and read transitions. The CY7C1354DV25 and CY7C1356DV25 are pin compatible with and functionally equivalent to ZBT devices.