The CY7C1353 is a 3.3V 256K by 18 SynchronousFlow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353 is equipped with the advanced No Bus Latency (NoBL TM) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions.The CY7C1353 is pin/functionally compatible to ZBTTM SRAMs MCM63Z819 and MT55L256L18F.