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Partname: | CY7C1351-40AC |
Description: | 128Kx36 Flow-Through SRAM with NoBL Architecture |
Manufacturer: | Cypress Semiconductor |
Datasheet: | PDF (183K). Click here to download *) |
The CY7C1351 is a 3.3V, 128K by 36 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351 is equipped with the advanced No Bus LatencyTM (NoBLTM) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write/Read transitions. The CY7C1351 is pin/functionally compatible to ZBT SRAMs IDT71V547, MT55L128L36F, and MCM63Z737. All synchronous inputs pass through input registers controlled by the rising edge of the clock.The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 11.0 ns (66-MHz device). |
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Click here to download CY7C1351-40AC Datasheet*) |
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