The CY7C1350F is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350F is equipped with the advanced No Bus LatencyTM (NoBLTM) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which, when deasserted, suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 2.8 ns (200-MHz device)