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Partname: | CY7C1350B |
Description: | 128Kx36 Pipelined SRAM with NoBL Architecture |
Manufacturer: | Cypress Semiconductor |
Datasheet: | PDF (200K). Click here to download *) |
The CY7C1350B is a 3.3V, 128K by 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350B is equipped with the advanced No Bus LatencyTM (NoBLTM) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent Write/Read transitions. The CY7C1350B is pin/functionally compatible |
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Click here to download CY7C1350B Datasheet*) |
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