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Partname:CY7C1319BV18-250BZXC
Description:18-Mbit DDR-II SRAM 4-Word Burst Architecture
Manufacturer:Cypress Semiconductor
Datasheet:PDF (479K).
Click here to download *)

The CY7C1317BV18, CY7C1917BV18, CY7C1319BV18, and CY7C1321BV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II (Double Data Rate) architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a two-bit burst counter. Addresses for Read and Write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with four 8-bit words in the case of CY7C1317BV18 and four 9-bit words in the case of CY7C1917BV18 that burst sequentially into or out of the device. The burst counter always starts with "00" internally in the case of CY7C1317BV18 and CY7C1917BV18. On CY7C1319BV18 and CY7C1321BV18, the burst counter takes in the last two significant bits of the external address and bursts four 18-bit words in the case of CY7C1319BV18, and four 36-bit words in the case of CY7C1321BV18, sequentially into or out of the device.

Click here to download CY7C1319BV18-250BZXC Datasheet
Click here to download CY7C1319BV18-250BZXC Datasheet
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