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Partname: | CY7C1312V18 |
Description: | Errata Document for CY7C1312V18 & CY7C1314V18 |
Manufacturer: | Cypress Semiconductor |
Datasheet: | PDF (47.5K). Click here to download *) |
The read address is provided on the rising edge of K The write address is provided on the rising edge of K# If the read and write address are the same, data is forwarded from the input port to the output port and the data from the memory array is ignored. This feature is called the data forwarding feature and it ensures that the most current data is always output from the device. In the event that address 7C is the only address that changes between the read address, and the write address in a given clock cycle, and if address 7C is changing from "1" to "0", then the data forwarding may be erroneously activated. The data from the memory array may be ignored and the data from the input bus may be improperly forwarded. |
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