The CY7C1303CV25 and CY7C1306CV25 are 2.5V Synchronous Pipelined SRAMs, equipped with QDRTM architecture. QDR architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. QDR architecture has separate data inputs and data outputs to completely eliminate the need to "turn-around" the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. The read address is latched on the rising edge of the K clock and the write address is latched on the rising edge of the K clock. Accesses to the QDR read and write ports are completely independent of one another. All accesses are initiated synchronously on the rising edge of the positive input clock (K). To maximize data throughput, both read and write ports are provided with DDR interfaces. Therefore, data can be transferred into the device on every rising edge of both input clocks (K and K) and out of the device on every rising edge of the output clock (C and C, or K and K when in single clock mode) thereby maximizing performance while simplifying system design. Each address location is associated with two 18-bit words (CY7C1303CV25), or 36-bit words (CY7C1306CV25) that burst sequentially into or out of the device.