The CY7C1303AV25 and CY7C1306AV25 are 2.5V Synchronous Pipelined SRAMs equipped with QDRTM architecture. QDR architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data inputs to support Write operations. Access to each port is accomplished through a common address bus. The Read address is latched on the rising edge of the K clock and the Write address is latched on the rising edge of K clock. QDR has separate data inputs and data outputs to completely eliminate the need to "turn-around" the data bus required with common I/O devices. Accesses to the CY7C1303AV25/ CY7C1306AV25 Read and Write ports are completely independent of one another. All accesses are initiated synchronously on the rising edge of the positive input clock (K). In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate (DDR) interfaces. Therefore, data can be transferred into the device on every rising edge of both input clocks (K and K) and out of the device on every rising edge of the output clock (C and C, or K and K when in single clock mode) thereby maximizing performance while simplifying system design. Each address location is associated with two 18-bit words (CY7C1303AV25) or two 36-bit words (CY7C1306AV25) that burst sequentially into or out of the device.