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Partname:CY7C1294DV18-200BZI
Description:9-Mbit QDR- II??? SRAM 2-Word Burst Architecture
Manufacturer:Cypress Semiconductor
Datasheet:PDF (993K).
Click here to download *)

The CY7C1292DV18 and CY7C1294DV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDRTM-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to "turn-around" the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. The Read address is latched on the rising edge of the K clock and the Write address is latched on the rising edge of the K clock. Accesses to the QDR-II Read and Write ports are completely independent of one another. In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate (DDR) interfaces. Each address location is associated with two 18-bit words (CY7C1292DV18) or 36-bit words (CY7C1294DV18) that burst sequentially into or out of the device. Since data can be transferred into and out of the device on every rising edge of both input clocks (K and K and C and C), memory bandwidth is maximized while simplifying system design by eliminating bus "turn-arounds."

Click here to download CY7C1294DV18-200BZI Datasheet
Click here to download CY7C1294DV18-200BZI Datasheet
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