The CY7C1246V18, CY7C1257V18, CY7C1248V18, and CY7C1250V18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II+ architecture. The DDR-II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of both K and K. Each address location is associated with two 8-bit words (CY7C1246V18), 9-bit words (CY7C1257V18), 18-bit words (CY7C1248V18), or 36-bit words (CY7C1250V18) that burst sequentially into or out of the device.