ChipDocs - Datasheet Source for Semiconductor and Electronic Circuit Components
More than
4 307 195 
components listed
Partname:CY7C1156V18-300BZXI
Description:18-Mbit QDR???-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
Manufacturer:Cypress Semiconductor
Datasheet:PDF (1.13M).
Click here to download *)

The CY7C1141V18, CY7C1156V18, CY7C1143V18, and CY7C1145V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDRTM-II+ architecture. QDR-II+ architecture consists of two separate ports to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR-II+ architecture has separate data inputs and data outputs to completely eliminate the need to "turn-around" the data bus required with common IO devices. Access to each port is accomplished through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the QDR-II+ read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are equipped with Double Data Rate (DDR) interfaces. Each address location is associated with four 8-bit words (CY7C1141V18), or 9-bit words (CY7C1156V18), or 18-bit words (CY7C1143V18), or 36-bit words (CY7C1145V18) that burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks K and K, memory bandwidth is maximized while simplifying system design by eliminating bus "turn-arounds".

Click here to download CY7C1156V18-300BZXI Datasheet
Click here to download CY7C1156V18-300BZXI Datasheet
*)
*)Datasheets downloading from ChipDocs is only for our members (paid service). REGISTER NOW for your membership.
Free Electronics Engineering Subscription
Win Win Circuit - PCB,PCBA,Touch Screen,LED Lighting
Win Win Circuit LTD. PCB, PCBA, LCD Module
www.wwteq.com
COPYRIGHT 1997-2024 ChipDocs  ALL RIGHT RESERVED