The CY7B9910 and CY7B9920 Low Skew Clock Buffers offer low-skew system clock distribution. These multiple-output clock drivers optimize the timing of high-performance computer systems. Eight individual drivers can each drive terminated transmission lines with impedances as low as 50 while delivering minimal and specified output skews and full-swing logic levels (CY7B9910 TTL or CY7B9920 CMOS). The completely integrated PLL allows "zero delay" capability. External divide capability, combined with the internal PLL, allows distribution of a low-frequency clock that can be multiplied by virtually any factor at the clock destination. This facility minimizes clock distribution difficulty while allowing maximum system clock speed and flexibility.